The present application relates to semiconductor fabrication, and more particularly to methods of forming a III-V compound semiconductor layer by aspect ratio trapping.
High mobility channel devices such as III-V compound semiconductors for n-type field effect transistors (nFETs) and silicon germanium (SiGe) or germanium (Ge) for p-type FET (pFET), have been proposed for future CMOS technology. Aspect ratio trapping has been developed as an effective way to grow high quality, low defect III-V compound semiconductors on a silicon (Si) wafer. Aspect ratio trapping utilizes high aspect ratio openings, such as trenches or holes, to trap dislocations, preventing dislocations from reaching the epitaxial film surface. However, conventional aspect ratio trapping has the following drawbacks: first of all, because high aspect ratio trenches are needed in aspect ratio trapping, the aspect ratio trapping process is applicable for forming fin structures. It is however rather difficult to form a large area planar structure using such an approach, rendering back biasing technique ineffective. Furthermore, the defective seed layer remains after the aspect ratio trapping growth processes. The defective seed layer needs to be isolated from the device layer, otherwise it can cause excessive device leakage. Therefore, there remains a need for a method of forming III-V compound semiconductors without suffering the above drawbacks of the conventional aspect ratio trapping.